The present invention concerns the fabrication of integrated circuits and pertains particularly to trench-diffusion corner rounding in a shallow-trench (STI) process.
Shallow trench isolation (STI) is gradually replacing conventional local oxidation of silicon (LOCOS) process for the formation of an isolation structure as technology is evolving to submicron geometry. STI has various advantages over the conventional LOCOS process. For example, STI allows for the planarization of the isolation structure. This results in better control of critical dimension (CD) when defining a gate stack of a transistor. Better control of CD when defining the gate stack results in better control of CD in further processing steps which occur after the gate stack is defined. For sub 0.25 micron CMOS processes, Shallow Trench Isolation (STI) is required because of its planarity, high packing density and low junction edge capacitance.
In a typical STI process, a buffer oxide of 10 to 20 nanometers (nm) is thermally grown on wafer substrate. A nitride of approximately 200 nm is deposited and then patterned with lithography and etched down to silicon. An etch that is selective to silicon (etches mostly silicon) is then used to etch a trench into the silicon. A liner oxide is thermally grown to anneal out any damage to the silicon and passivate the silicon. Next, an oxide that is considerably thicker than the trench depth is deposited. The wafer is then subjected to a chemical-mechanical (CMP) polishing that stops when it reaches the nitride. The nitride is then stripped, along with the buffer oxide underneath, thereby forming the shallow trench isolation.
For the above-described STI processing scheme, the sharp corner where the trench side wall meets the silicon surface causes many problems with device performance, yield, and reliability. See, for example, P. Sallagoity, et al. "Analysis of Width Edge Effects in Advanced Isolation Schemes for Deep Submicron CMOS Technologies", IEEE Trans. Elect. Devices. Vol. 43, No. 11, November 1996.
For this reason, the top corner of the trench is rounded in order to achieve stable device performance (no kink in the subthreshold slope), reduce inverse narrow width effects and maintain good gate oxide integrity and low junction leakage.
Many techniques have been tried to round the top corner both before and after Chemo-Mechanical Polishing (CMP). The pre-CMP rounding techniques have included Hydrogen annealing (S. Matsuda, et al., Novel Corner Rounding Process for Shallow Trench Isolation utilizing MSTS (Micro-Structure Transformation of Silicon), IEDM Technical Digest, pp. 137-140, 1998) and liner oxidation (see M. Nandakumar, et al., Shallow Trench Isolation for advanced VLSI CMOS Technologies, IEDM Technical Digest, pp. 133-136, 1998) that involves wet or dry oxidation at the proper temperature, time, ambient, and pre-clean. The post-CMP rounding techniques have involved high temperature wet oxidation, but if improperly designed can generate stress and lead to dislocation formation in the high stress areas. See F. Nouri, et al., An Optimized Shallow Trench Isolation for sub 0.18 .mu.m ASIC Technologies, Proc. of Microelectronic Device Technology, SPIE Vol. 3506. pp. 156-166, 1998; and, C. P. Chang, et al., A Highly Manufacturable Corner Rounding Solution for 0.18 .mu.m Shallow Trench Isolation, IEDM Technical Digest, pp. 661-664, 1997.